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lt3470 1 3470fd typical a pplica t ion fea t ures a pplica t ions descrip t ion micropower buck regulator with integrated boost and catch diodes the lt ? 3470 is a micropower step-down dc/dc con - verter that integrates a 300ma power switch, catch diode and boost diode into low profile 3mm 2mm dd and thinsot? packages. the lt3470 combines burst mode and continuous operation to allow the use of tiny induc- tor and capacitors while providing a low ripple output to loads of up to 200ma. with its wide input range of 4v to 40v, the lt3470 can regulate a wide variety of power sources, from 2-cell li - ion batteries to unregulated wall transformers and lead-acid batteries. quiescent current in regulation is just 26a in a typical application while a zero current shutdown mode disconnects the load from the input source, simplifying power management in battery-powered systems. fast current limiting and hysteretic control protects the lt3470 and external components against shorted outputs, even at 40v input. l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. efficiency and power loss vs load current n low quiescent current: 26a at 12v in to 3.3v out n integrated boost and catch diodes n input range: 4v to 40v n low output ripple: <10mv n < 1a in shutdown mode n output voltage: 1.25v to 16v n 200ma output current n hysteretic mode control C low ripple burst mode ? operation at light loads C continuous operation at higher loads n solution size as small as 50mm 2 n low profile (0.75mm) 3mm 2mm thermally enhanced 8-lead dd and 1mm thinsot packages n automotive battery regulation n power for portable products n distributed supply regulation n industrial supplies n wall transformer regulation load current (ma) 30 efficiency (%) power loss (mw) 40 60 80 90 0.1 10 100 3470 ta02 20 1 70 50 10 1 1000 100 10 0.1 v in = 12v v in boost lt3470 sw shdn 0.22f 22pf 22f 2.2f 3470 ta01a v in 7v to 40v v out 5v 200ma 604k 1% 200k 1% 33h bias fb gnd off on
lt3470 2 3470fd a bsolu t e maxi m u m r a t ings v in , shdn voltage ................................................... 4 0v boost pin voltage .................................................. 47 v boost pin above sw pin ........................................ 25v f b voltage .................................................................. 5v b ias voltage ............................................................. 25 v sw voltage ................................................................ v in maximum junction temperature lt3470e, lt3470i ............................................. 125 c lt3470h ........................................................... 15 0c (note 1) o r d er i n f or m a t ion operating temperature range (note 2) lt3470e ............................................... C 40c to 85c lt3470i ............................................. C 40c to 125c lt3470h ............................................ C 40c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) .................. 3 00c top view 9 ddb8 package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1fb bias boost sw shdn nc v in gnd v ja = 180c/w exposed pad (pin 9) is ground (must be soldered to pcb) shdn 1 nc 2 v in 3 gnd 4 8 fb 7 bias 6 boost 5 sw top view ts8 package 8-lead plastic tsot-23 v ja = 140c/w p in c on f igura t ion lead free finish tape and reel part marking package description temperature range lt3470eddb#pbf lt3470eddb#trpbf lbpn 8-lead (3mm w 2mm) plastic dfn C40c to 85c lt3470iddb#pbf lt3470iddb#trpbf lbpp 8-lead (3mm w 2mm) plastic dfn C40c to 125c lt3470hddb#pbf lt3470hddb#trpbf lcnr 8-lead (3mm w 2mm) plastic dfn C40c to 150c lt3470ets8#pbf lt3470ets8#trpbf ltbdm 8-lead plastic tsot-23 C40c to 85c lt3470its8#pbf lt3470its8#trpbf ltbpw 8-lead plastic tsot-23 C40c to 125c LT3470HTS8#pbf LT3470HTS8#trpbf ltcnq 8-lead plastic tsot-23 C40c to 150c lead based finish tape and reel part marking package description temperature range lt3470eddb lt3470eddb#tr lbpn 8-lead (3mm w 2mm) plastic dfn C40c to 85c lt3470iddb lt3470iddb#tr lbpp 8-lead (3mm w 2mm) plastic dfn C40c to 125c lt3470hddb lt3470hddb#tr lcnr 8-lead (3mm w 2mm) plastic dfn C40c to 150c lt3470ets8 lt3470ets8#tr ltbdm 8-lead plastic tsot-23 C40c to 85c lt3470its8 lt3470its8#tr ltbpw 8-lead plastic tsot-23 C40c to 125c LT3470HTS8 LT3470HTS8#tr ltcnq 8-lead plastic tsot-23 C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
lt3470 3 3470fd the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 10v, v shdn = 10v, v boost = 15v, v bias = 3v unless otherwise specified. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3470e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the lt3470i specifications are guaranteed over the C40c to 125c temperature range. lt3470h specifications are guaranteed over C40c to 150c temperature range. note 3: bias current flows out of the fb pin. note 4: this is the minimum voltage across the boost capacitor needed to guarantee full saturation of the switch. note 5: this parameter is assured by design and correlation with statistical process controls. e lec t rical c harac t eris t ics parameter conditions min typ max units minimum input voltage 4 v quiescent current from v in v shdn = 0.2v v bias = 3v, not switching v bias = 0v, not switching 0.1 10 35 0.5 18 50 a a a quiescent current from bias v shdn = 0.2v v bias = 3v, not switching v bias = 0v, not switching 0.1 25 0.1 0.5 60 1.5 a a a fb comparator trip voltage v fb falling 1.228 1.250 1.265 v fb pin bias current (note 3) v fb = 1v, e- and i-grade 35 35 80 150 na na h-grade 35 225 na fb voltage line regulation 4v < v in < 40v 0.0006 0.01 %/v minimum switch off-time (note 5) 500 ns switch leakage current 0.7 1.5 a switch v cesat i sw = 100ma (ts8 package) i sw = 100ma (dd8 package) 215 215 300 mv mv switch top current limit v fb = 0v 250 325 435 ma switch bottom current limit v fb = 0v 225 ma catch schottky drop i sh = 100ma (ts8 package) i sh = 100ma (dd8 package) 630 630 775 mv mv catch schottky reverse leakage v sw = 10v 0.2 2 a boost schottky drop i sh = 30ma 650 775 mv boost schottky reverse leakage v sw = 10v, v bias = 0v 0.2 2 a minimum boost voltage (note 4) 1.7 2.2 v boost pin current i sw = 100ma 7 12 ma shdn pin current v shdn = 2.5v 1 5 a shdn input voltage high 2.5 v shdn input voltage low 0.2 v
lt3470 4 3470fd typical p er f or m ance c harac t eris t ics efficiency, v out = 3.3v efficiency, v out = 5v v fb vs temperature top and bottom switch current limits (v fb = 0v) vs temperature v in quiescent current vs temperature bias quiescent current (bias > 3v) vs temperature shdn bias current vs temperature fb bias current (v fb = 1v) vs temperature load current (ma) 50 efficiency (%) 70 90 40 60 80 0.1 10 100 3470 g01 30 1 l = toko d52lc 47h t a = 25c v in = 7v v in = 12v v in = 36v v in = 24v load current (ma) 50 efficiency (%) 70 90 40 60 80 0.1 10 100 3470 g02 30 1 l = toko d52lc 47h t a = 25c v in = 12v v in = 36v v in = 24v temperature (c) ?50 1.240 v fb (v) 1.245 1.250 1.255 1.260 ?25 0 25 50 3470 g03 75 100 125 temperature (c) ?50 current limit (ma) 350 25 3470 g04 200 100 ?25 0 50 50 0 400 300 250 150 75 100 150125 temperature (c) ?50 ?25 0 v in current (a) 20 50 0 50 75 3470 g05 10 40 30 25 100 150125 bias < 3v bias > 3v temperature (c) ?50 bias current (a) 20 25 30 25 75 3470 g06 15 10 ?25 0 50 100 150125 5 0 temperature (c) ?50 0 shdn current (a) 1 3 4 5 50 9 3470 g07 2 0 ?25 75 100 25 150125 6 7 8 v shdn = 36v v shdn = 2.5v temperature (c) ?50 ?25 0 fb current (na) 20 60 50 0 50 75 3470 g08 10 40 30 25 100 150125
lt3470 5 3470fd typical p er f or m ance c harac t eris t ics fb bias current (v fb = 0v) vs temperature switch v cesat (i sw = 100ma) vs temperature boost diode v f (i f = 50ma) vs temperature catch diode v f (i f = 100ma) vs temperature diode leakage (v r = 36v) vs temperature switch v cesat boost pin current catch diode forward voltage temperature (c) ?50 fb current (a) 80 100 120 25 75 3470 g09 60 40 ?25 0 50 100 150125 20 0 temperature (c) ?50 switch v cesat (mv) 200 250 300 25 75 3470 g10 150 100 ?25 0 50 100 150125 50 0 temperature (c) ?50 schottky v f (v) 0.7 25 3470 g11 0.4 0.2 ?25 0 50 0.1 0 0.8 0.6 0.5 0.3 75 100 150125 temperature (c) ?50 0.4 0.5 0.7 25 75 3470 g12 0.3 0.2 ?25 0 50 100 150125 0.1 0 0.6 schottky v f (v) temperature (c) ?50 ?25 0 schottky diode leakage (a) 30 60 0 50 75 3470 g13 20 15 10 50 40 25 55 5 45 35 25 100 150125 catch boost switch current (ma) 0 400 500 700 300 3470 g14 300 200 100 200 400 100 0 600 switch v cesat (mv) switch current (ma) 0 8 10 14 300 3470 g15 6 4 100 200 400 2 0 12 boost pin current (ma) catch diode current (ma) 0 schottky v f (v) 0.4 0.6 400 3470 g16 0.2 0 100 200 300 1.0 0.8
lt3470 6 3470fd shdn (pin 1/pin 8): the shdn pin is used to put the lt3470 in shutdown mode. tie to ground to shut down the lt3470. apply 2v or more for normal operation. if the shutdown feature is not used, tie this pin to the v in pin. nc (pin 2/pin 7): this pin can be left floating or connected to v in . v in (pin 3/pin 6): the v in pin supplies current to the lt3470s internal regulator and to the internal power switch. this pin must be locally bypassed. gnd (pin 4/pin 5): tie the gnd pin to a local ground plane below the lt3470 and the circuit components. return the feedback divider to this pin. sw (pin 5/pin 4): the sw pin is the output of the internal power switch. connect this pin to the inductor, catch diode and boost capacitor. boost (pin 6/pin 3): the boost pin is used to provide a drive voltage, which is higher than the input voltage, to the internal bipolar npn power switch. bias (pin 7 /pin 2): the bias pin connects to the internal boost schottky diode and to the internal regulator. tie to v out when v out > 2v or to v in otherwise. when v bias > 3v the bias pin will supply current to the internal regulator. fb (pin 8 /pin 1): the lt3470 regulates its feedback pin to 1.25v. connect the feedback resistor divider tap to this pin. set the output voltage according to v out = 1.25v (1 + r1/r2) or r1 = r2 (v out /1.25 C 1). exposed pad ( dd, pin 9): ground. must be soldered to pcb. boost diode forward voltage minimum input voltage, v out = 3.3v minimum input voltage, v out = 5v typical p er f or m ance c harac t eris t ics boost diode current (ma) 0 schottky v f (v) 500 600 700 200 3470 g17 400 300 0 50 100 150 100 200 900 800 load current (ma) 0 3.0 input voltage (v) 3.5 4.0 4.5 5.0 5.5 6.0 50 100 150 200 3470 g18 t a = 25c v in to start v in to run load current (ma) 0 input voltage (v) 6 7 200 3470 g19 5 4 50 100 150 8 t a = 25c v in to start v in to run p in func t ions (thinsot/dd)
lt3470 7 3470fd b lock diagra m ? + ? + r q s q 500ns one shot v ref 1.25v burst mode detect sw gnd 3470 bd fb r2 r1 shdn enable v in v in nc bias boost l1 c2 c3 v out g m c1
lt3470 8 3470fd figure 1. operating waveforms of the lt3470 converting 12v to 5v using a 33h inductor and 10f output capacitor the lt3470 uses a hysteretic control scheme in conjunction with burst mode operation to provide low output ripple and low quiescent current while using a tiny inductor and capacitors. operation can best be understood by studying the block diagram. an error amplifier measures the output voltage through an external resistor divider tied to the fb pin. if the fb voltage is higher than v ref , the error amplifier will shut off all the high power circuitry, leaving the lt3470 in its micropower state. as the fb voltage falls, the error amplifier will enable the power section, causing the chip to begin switching, thus delivering charge to the output capacitor. if the load is light the part will alternate between micropower and switching states to keep the output in regulation (see figure 1a). at higher loads the part will switch continuously while the error amp servos the top and bottom current limits to regulate the fb pin voltage to 1.25v (see figure 1b). the switching action is controlled by an rs latch and two current comparators as follows: the switch turns on, and the current through it ramps up until the top current comparator trips and resets the latch causing the switch to turn off. while the switch is off, the inductor current ramps down through the catch diode. when both the bot- tom current comparator trips and the minimum off-time one-shot expires, the latch turns the switch back on thus completing a full cycle. the hysteretic action of this control scheme results in a switching frequency that depends on inductor value, input and output voltage. since the switch only turns on when the catch diode current falls below threshold, the part will automatically switch slower to keep inductor current under control during start-up or short-circuit conditions. the switch driver operates from either the input or from the boost pin. an external capacitor and internal diode is used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to fully saturate the internal bipolar npn power switch for efficient operation. if the shdn pin is grounded, all internal circuits are turned off and v in current reduces to the device leakage current, typically a few na. (1a) burst mode operation (1b) continuous operation v out 20mv/div i l 100ma/div 1ms/div v out 20mv/div i l 100ma/div 5s/div 3470 f01a no load 10ma load v out 20mv/div i l 100ma/div 1s/div v out 20mv/div i l 100ma/div 1s/div 3470 f1b 200ma load 150ma load o pera t ion
lt3470 9 3470fd a pplica t ions i n f or m a t ion input voltage range the minimum input voltage required to generate a par - ticular output voltage in an lt3470 application is limited by either its 4v undervoltage lockout or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc = v out + v d v in ? v sw + v d where v d is the forward voltage drop of the catch diode (~0.6v) and v sw is the voltage drop of the internal switch at maximum load (~0.4v). given dc max = 0.90, this leads to a minimum input voltage of: v in(min) = v out + v d dc max ? ? ? ? ? ? + v sw ? v d this analysis assumes the part has started up such that the capacitor tied between the boost and sw pins is charged to more than 2v. for proper start-up, the minimum input voltage is limited by the boost circuit as detailed in the section boost pin considerations. the maximum input voltage is limited by the absolute maximum v in rating of 40v, provided an inductor of suf - ficient value is used. inductor selection the switching action of the lt3470 during continuous operation produces a square wave at the sw pin that results in a triangle wave of current in the inductor. the hysteretic mode control regulates the top and bottom current limits (see electrical characteristics) such that the average inductor current equals the load current. for safe operation, it must be noted that the lt3470 cannot turn the switch on for less than ~150ns. if the inductor is small and the input voltage is high, the current through the switch may exceed safe operating limit before the lt3470 is able to turn off. to prevent this from happening, the following equation provides a minimum inductor value: l min = v in(max) ? t on-time(min) i max where v in(max) is the maximum input voltage for the ap- plication, t on-time(min) is ~150ns and i max is the maximum allowable increase in switch current during a minimum switch on-time (150ma). while this equation provides a safe inductor value, the resulting application circuit may switch at too high a frequency to yield good efficiency. it is advised that switching frequency be below 1.2mhz during normal operation: f = 1? dc ( ) v d + v out ( ) l ? ? i l where f is the switching frequency, ?i l is the ripple current in the inductor (~150ma), v d is the forward voltage drop of the catch diode, and v out is the desired output voltage. if the application circuit is intended to operate at high duty cycles (v in close to v out ), it is important to look at the calculated value of the switch off-time: t off-time = 1? dc f the calculated t off-time should be more than lt3470s minimum t off-time (see electrical characteristics), so the application circuit is capable of delivering full rated output current. if the full output current of 200ma is not required, the calculated t off-time can be made less than minimum t off-time possibly allowing the use of a smaller inductor. see table 1 for an inductor value selection guide. table 1. recommended inductors for loads up to 200ma v out v in up to 16v v in up to 40v 2.5v 10h 33h 3.3v 10h 33h 5v 15h 33h 12v 33h 47h choose an inductor that is intended for power applications. table 2 lists several manufacturers and inductor series. for robust output short-circuit protection at high v in (up to 40v) use at least a 33h inductor with a minimum 450ma saturation current. if short-circuit performance is not required, inductors with i sat of 300ma or more may
lt3470 10 3470fd table 2. inductor vendors vendor url part series inductance range (h) size (mm) coilcraft www.coilcraft.com do1605 me3220 do3314 10 to 47 10 to 47 10 to 47 1.8 5.4 4.2 2.0 3.2 2.5 1.4 3.3 3.3 sumida www.sumida.com cr32 cdrh3d16/hp cdrh3d28 cdrh2d18/hp 10 to 47 10 to 33 10 to 47 10 to 15 3.0 3.8 4.1 1.8 4.0 4.0 3.0 4.0 4.0 2.0 3.2 3.2 toko www.tokoam.com db320c d52lc 10 to 27 10 to 47 2.0 3.8 3.8 2.0 5.0 5.0 wrth elektronik www.we-online.com we-pd2 typ s we-tpc typ s 10 to 47 10 to 22 3.2 4.0 4.5 1.6 3.8 3.8 coiltronics www.cooperet.com sd10 10 to 47 1.0 5.0 5.0 murata www.murata.com lqh43c lqh32c 10 to 47 10 to 15 2.6 3.2 4.5 1.6 2.5 3.2 a pplica t ions i n f or m a t ion be used. it is important to note that inductor saturation current is reduced at high temperaturessee inductor vendors for more information. input capacitor step-down regulators draw current from the input sup- ply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the v in pin of the lt3470 and to force this switching current into a tight local loop, minimizing emi. the input capacitor must have low impedance at the switching frequency to do this effectively. a 1f to 2.2f ceramic capacitor satisfies these requirements. if the input source impedance is high, a larger value ca - pacitor may be required to keep input ripple low. in this case, an electrolytic of 10f or more in parallel with a 1f ceramic is a good combination. be aware that the input capacitor is subject to large surge currents if the lt3470 circuit is connected to a low impedance supply, and that some electrolytic capacitors (in particular tantalum) must be specified for such use. output capacitor and output ripple the output capacitor filters the inductors ripple current and stores energy to satisfy the load current when the lt3470 is quiescent. in order to keep output voltage ripple low, the impedance of the capacitor must be low at the lt3470s switching frequency. the capacitors equivalent series resistance (esr) determines this impedance. choose one with low esr intended for use in switching regulators. the contribution to ripple voltage due to the esr is ap- proximately i lim ? esr. esr should be less than ~150m. the value of the output capacitor must be large enough to accept the energy stored in the inductor without a large change in output voltage. setting this voltage step equal to 1% of the output voltage, the output capacitor must be: c out > 50 s l s i lim v out ? ? ? ? ? ? 2 where i lim is the top current limit with v fb = 0v (see elec- trical characteristics). for example, an lt3470 producing 3.3v with l = 33h requires 22f. the calculated value can be relaxed if small circuit size is more important than low output ripple. sanyos poscap series in b-case and provides very good performance in a small package for the lt3470. similar performance in traditional tantalum capacitors requires a larger package (c-case). with a high quality capacitor filtering the ripple current from the inductor, the output voltage ripple is determined by the delay in the lt3470s feedback comparator. this ripple can be reduced further by adding a small (typically 22pf) phase lead capacitor between the output and the feedback pin.
lt3470 11 3470fd applica t ions in f or m a t ion ceramic capacitors ceramic capacitors are small, robust and have very low esr. however, ceramic capacitors can cause problems when used with the lt3470. not all ceramic capacitors are suitable. x5r and x7r types are stable over temperature and applied voltage and give dependable service. other types, including y5v and z5u have very large temperature and voltage coefficients of capacitance. in an application circuit they may have only a small fraction of their nominal capacitance resulting in much higher output voltage ripple than expected. ceramic capacitors are piezoelectric. the lt3470s switch - ing frequency depends on the load current, and at light loads the lt3470 can excite the ceramic capacitor at audio frequencies, generating audible noise. since the lt3470 operates at a lower current limit during burst mode opera - tion, the noise is typically very quiet to a casual ear. if this audible noise is unacceptable, use a high performance electrolytic capacitor at the output. the input capacitor can be a parallel combination of a 2.2f ceramic capacitor and a low cost electrolytic capacitor. a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the lt3470. a ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. if the lt3470 circuit is plugged into a live supply, the input volt - age can ring to twice its nominal value, possibly exceeding the lt3470s rating. this situation is easily avoided; see the hot-plugging safely section. boost and bias pin considerations capacitor c3 and the internal boost schottky diode (see block diagram) are used to generate a boost voltage that is higher than the input voltage. in most cases a 0.22f capacitor will work well. figure 2 shows two ways to ar - range the boost circuit. the boost pin must be more than 2.5v above the sw pin for best efficiency. for outputs of 3.3v and above, the standard circuit (figure 2a) is best. for outputs between 2.5v and 3v, use a 0.47f. for lower output voltages the boost diode can be tied to the input figure 2. two circuits for generating the boost voltage table 3. capacitor vendors vendor phone url part series comments panasonic (714) 373-7366 www.panasonic.com ceramic, polymer, tantalum eef series kemet (864) 963-6300 www.kemet.com ceramic, tantalum t494, t495 sanyo (408) 749-9714 www.sanyovideo.com ceramic, polymer, tantalum poscap murata (404) 436-1300 www.murata.com ceramic avx www.avxcorp.com ceramic, tantalum tps series taiyo yuden (864) 963-6300 www.taiyo-yuden.com ceramic v in boost lt3470 (2a) (2b) sw c3 0.22f v in v out v boost ? v sw ? v out max v boost ? v in + v out bias gnd v in boost lt3470 sw bias c3 0.22f v in v out 3470 f02 v boost ? v sw ? v in max v boost ? 2v in gnd
lt3470 12 3470fd figure 3. the minimum input voltage depends on output voltage, load current and boost circuit minimum input voltage, v out = 3.3v minimum input voltage, v out = 5v figure 4. diode d1 prevents a shorted input from discharging a backup battery tied to the output; it also protects the circuit from a reversed input. the lt3470 runs only when the input is present hot-plugging safely a pplica t ions i n f or m a t ion (figure 2b). the circuit in figure 2a is more efficient because the boost pin current and bias pin quiescent current comes from a lower voltage source. you must also be sure that the maximum voltage ratings of the boost and bias pins are not exceeded. the minimum operating voltage of an lt3470 application is limited by the undervoltage lockout (4v) and by the maximum duty cycle as outlined in a previous section. for proper start-up, the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, or the lt3470 is turned on with its shdn pin when the output is already in regulation, then the boost capacitor may not be fully charged. the plots in figure 3 show minimum v in to start and to run. at light loads, the inductor current becomes discontinuous and the effective duty cycle can be very high. this reduces the minimum input voltage to approximately 300mv above v out . at higher load currents, the inductor current is continuous and the duty cycle is limited by the maximum duty cycle of the lt3470, requiring a higher input voltage to maintain regulation. shorted input protection if the inductor is chosen so that it wont saturate exces- sively at the top switch current limit maximum of 450ma, an lt3470 buck regulator will tolerate a shorted output even if v in = 40v. there is another situation to consider in systems where the output will be held high when the input to the lt3470 is absent. this may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode or-ed with the lt3470s output. if the v in pin is allowed to float and the shdn pin is held high (either by a logic signal or because it is tied to v in ), then the lt3470s internal circuitry will pull its quiescent current through its sw pin. this is fine if your system can tolerate a few ma in this state. if you ground the shdn pin, the sw pin current will drop to es- sentially zero. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the lt3470 can pull large currents from the output through the sw pin and the v in pin. figure 4 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. load current (ma) 0 3.0 input voltage (v) 3.5 4.0 4.5 5.0 5.5 6.0 50 100 150 200 3470 g18 t a = 25c v in to start v in to run load current (ma) 0 input voltage (v) 6 7 200 3470 g19 5 4 50 100 150 8 t a = 25c v in to start v in to run v in boost lt3470 sot-23 sw shdn 3470 f04 v in 100k d1 1m v out backup bias fb gnd
lt3470 13 3470fd applica t ions in f or m a t ion pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. note that large, switched currents flow in the power switch, the internal catch diode and the input capacitor. the loop formed by these components should be as small as possible. further - more, the system ground should be tied to the regulator ground in only one place; this prevents the switched cur - rent from injecting noise into the system ground. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor c2. additionally, the sw and boost nodes should be kept as small as possible. unshielded inductors can induce noise in the feedback path resulting in instability and increased output ripple. to avoid this problem, use vias to route the v out trace under the ground plane to the feedback divider (as shown in figure 5). finally, keep the fb node as small as possible so that the ground pin and ground traces will shield it from the sw and boost nodes. figure 5 shows component placement with trace, ground plane and via locations. include vias near the gnd pin, or pad, of the lt3470 to help remove heat from the lt3470 to the ground plane. figure 5. a good pcb layout ensures proper, low emi operation shdn v in v out (5a) (5b) v out 3470 f05 gnd shdn v in gnd c1 c2 vias to feedback divider vias to local ground plane outline of local ground plane
lt3470 14 3470fd a pplica t ions i n f or m a t ion hot-plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of lt3470. however, these capacitors can cause problems if the lt3470 is plugged into a live supply (see linear technology application note 88 for a complete discussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an under damped tank circuit, and the voltage at the v in pin of the lt3470 can ring to twice the nominal input voltage, possibly exceeding the lt3470s rating and damaging the part. if the input supply is poorly controlled or the user will be plugging the lt3470 into an energized supply, the input network should be designed to prevent this overshoot. figure 6 shows the waveforms that result when an lt3470 circuit is connected to a 24v supply through six feet of 24-gauge twisted pair. the first plot is the response with a 2.2f ceramic capacitor at the input. the input voltage rings as high as 35v and the input current peaks at 20a. one method of damping the tank circuit is to add another capacitor with a series resistor to the circuit. in figure 6b an aluminum electrolytic capacitor has been added. this capacitors high equivalent series resistance damps the circuit and eliminates the voltage overshoot. the extra capacitor improves low frequency ripple filtering and can slightly improve the efficiency of the circuit, though it is likely to be the largest component in the circuit. an alterna - tive solution is shown in figure 6c. a 1 resistor is added in series with the input to eliminate the voltage overshoot (it also reduces the peak input current). a 0.1f capacitor improves high frequency filtering. this solution is smaller and less expensive than the electrolytic capacitor. for high input voltages its impact on efficiency is minor, reducing efficiency less than one half percent for a 5v output at full load operating from 24v. high temperature considerations the die junction temperature of the lt3470 must be lower than the maximum rating of 125c (150c for the h-grade). this is generally not a concern unless the ambi- ent temperature is above 85c. for higher temperatures, care should be taken in the layout of the circuit to ensure good heat sinking of the lt3470. the maximum load current should be derated as the ambient temperature approaches the maximum junction rating. the die tem- perature is calculated by multiplying the lt3470 power dissipation by the thermal resistance from junction to ambient. power dissipation within the lt3470 can be estimated by calculating the total power loss from an efficiency measurement. thermal resistance depends on the layout of the circuit board and choice of package. the dd package with the exposed pad has a thermal resistance of approximately 80c/w while the thinsot is approximately 150c/w. finally, be aware that at high ambient temperatures the internal schottky diode will have significant leakage current (see typical performance characteristics) increasing the quiescent current of the lt3470 converter.
lt3470 15 3470fd applica t ions in f or m a t ion figure 6. a well chosen input network prevents input voltage overshoot and ensures reliable operation when the lt3470 is connected to a live supply + lt3470 2.2f v in 10v/div i in 10a/div 10s/div v in closing switch simulates hot plug i in (6a) (6b) (6c) low impedance energized 24v supply stray inductance due to 6 feet (2 meters) of twisted pair + lt3470 2.2f 10f 35v ai.ei. lt3470 2.2f 0.1f 1 3470 f06
lt3470 16 3470fd 3.3v step-down converter 5v step-down converter 2.5v step-down converter v in boost lt3470 sw shdn c3 0.22f, 6.3v 22pf c2 22f 3470 ta03 c1 1f v in 5.5v to 40v v out 3.3v 200ma r1 324k r2 200k c1: tdk c3216jb1h105m c2: ce jmk316 bj226ml-t l1: toko a993as-270m=p3 l1 33h bias fb gnd off on v in boost lt3470 sw shdn c3 0.22f, 6.3v 22pf c2 22f 3470 ta04 c1 1f v in 7v to 40v v out 5v 200ma r1 604k r2 200k l1 33h bias fb gnd off on c1: tdk c3216jb1h105m c2: ce jmk316 bj226ml-t l1: toko a914byw-330m=p3 typical a pplica t ions 1.8v step-down converter 12v step-down converter v in boost lt3470 sw shdn c3 0.47f, 6.3v 22pf c2 22f 3470 ta07 c1 1f v in 4.7v to 40v v out 2.5v 200ma r1 200k r2 200k c1: tdk c3216jb1h105m c2: tdk c2012jb0j226m l1: sumida cdrh3d28 l1 33h bias fb gnd off on v in boost lt3470 sw shdn bias c3 0.22f, 25v 22pf c2 22f 3470 ta05 c1 1f v in 4v to 23v v out 1.8v 200ma r1 147k r2 332k l1 22h fb gnd off on c1: tdk c3216jb1h105m c2: tdk c2012jb0j226m l1: murata lqh32cn150k53 v in boost lt3470 sw shdn c3 0.22f, 16v 22pf c2 10f 3470 ta06 c1 1f v in 15v to 34v v out 12v 200ma r1 866k r2 100k c1: tdk c3216jb1h105m c2: tdk c3216jb1c106m l1: murata lqh32cn150k53 l1 33h bias fb gnd off on
lt3470 17 3470fd p ackage descrip t ion ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
lt3470 18 3470fd p ackage descrip t ion ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.50 bsc please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
lt3470 19 3470fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number d 09/11 corrected lead-based tape and reel part numbers in the order information section. 2 (revision history begins at rev d)
lt3470 20 3470fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2004 lt 0911 rev d ? printed in usa r ela t e d p ar t s part number description comments lt1616 25v, 500ma (i out ), 1.4mhz, high efficiency step-down dc/dc converter v in = 3.6v to 25v, v out = 1.25v, i q = 1.9ma, i sd < 1a, thinsot package lt1676 60v, 440ma (i out ), 100khz, high efficiency step-down dc/dc converter v in = 7.4v to 60v, v out = 1.24v, i q = 3.2ma, i sd = 2.5a, s8 package lt1765 25v, 2.75a (i out ), 1.25mhz, high efficiency step-down dc/dc converter v in = 3v to 25v, v out = 1.2v, i q = 1ma, i sd = 15a, s8, tssop16e packages lt1766 60v, 1.2a (i out ), 200khz, high efficiency step-down dc/dc converter v in = 5.5v to 60v, v out = 1.2v, i q = 2.5ma, i sd = 25a, tssop16/e package lt1767 25v, 1.2a (i out ), 1.25mhz, high efficiency step-down dc/dc converter v in = 3v to 25v; v out = 1.2v, i q = 1ma, i sd = 6a, ms8/e packages lt1776 40v, 550ma (i out ), 200khz, high efficiency step-down dc/dc converter v in = 7.4v to 40v; v out = 1.24v, i q = 3.2ma, i sd = 30a, n8, s8 packages lt c ? 1877 600ma (i out ), 550khz, synchronous step-down dc/dc converter v in = 2.7v to 10v; v out = 0.8v, i q = 10a, i sd 1a, ms8 package ltc1879 1.2a (i out ), 550khz, synchronous step-down dc/dc converter v in = 2.7v to 10v; v out = 0.8v, i q = 15a, i sd 1a, tssop16 package lt1933 36v, 600ma, 500khz, high efficiency step-down dc/dc converter v in = 3.6v to 36v; v out = 1.25v, i q = 2.5a, i sd 1a, ??? package lt1934 34v, 250ma (i out ), micropower, step-down dc/dc converter v in = 3.2v to 34v; v out = 1.25v, i q = 12a, i sd 1a, ??? package lt1956 60v, 1.2a (i out ), 500khz, high efficiency step-down dc/dc converter v in = 5.5v to 60v, v out = 1.2v, i q = 2.5ma, i sd = 25a, tssop16/e package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down dc/dc converter v in = 2.7v to 6v, v out = 0.8v, i q = 20a, i sd 1a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converter v in = 2.5v to 5.5v, v out = 0.6v, i q = 20a, i sd 1a, thinsot package ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter v in = 2.5v to 5.5v, v out = 0.8v, i q = 60a, i sd 1a, ms package ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter v in = 2.5v to 5.5v, v out = 0.8v, i q = 60a, i sd 1a, tssop16e package ltc3430 60v, 2.75a (i out ), 200khz, high efficiency step-down dc/dc converter v in = 5.5v to 60v, v out = 1.2v, i q = 2.5ma, i sd = 30a, tssop16e package

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